Senior Principal Engineer - IP Verification

Digital IP Verification Engineers [14 to 20 yrs exp]

Job Opportunity: Seeking highly motivated, energetic, team-oriented Individual contributor willing to take the challenge of delivering the first pass success of complex IPs using the latest advanced verification languages and methodology.

The person would be working with experienced and motivated team of global stakeholders in Systems, Design, DFT, Mixed Signal and other local/remote teams to address the verification challenges in the context of the IP, SubSystem, and overall system, through the use of simulation, hardware modeling, formal verification and active participation in pre/post silicon validation.

Key Responsibilities

• Evaluate and deploy the evolving verification methodologies to handle increasingly complex IP/SubSystem designs within aggressive, market-driven schedules.
• Own and ensure quality adherence during all stages of the project cycle. Ability to carry out a thorough analysis of existing processes, recommend and implement process improvements to ensure ‘Zero Defect’ IPs/SubSystems.
• Building and Influencing technological innovations for self and in team environment within team and with global stake holder across sites.
• Hands on and ability to work well as part of a team both locally, and with remote or multi-site teams.

Key Skills

• Self starter with 18+ years of experience on IP / Sub-system verification on multimillion Gate and complex Design with multiple clocks with minimal supervision
• Testbench and Testplan development to ensure thorough functional verification, and performance aspects of the IP along with Features traceability.
• Experience in microcontroller architecture working with ARM cores, protocols like AHB/AMBA, AXI, Memory (Flash, SRAM,DDR) and memory controllers
• Experience in domains like automotive Graphics / Vision accelerators, Slow and High Speed Serial IP controllers, Networking protocols like Ethernet, would be an added advantage
• Must have experience and strong working knowledge of HVLs like (UVM/SV/C++), HDLs (Verilog/VHDL), PLI/DPI, simulators (NCSim/VCS/ModelSim/Questa).
• Must have experience in end to end IP verification project cycle, including Testbench Strategies, TB development, simulation debugs.
• Good Exposure to formal verification methodology, assertions/SVA, functional coverage, gate level simulations, verification planner and regression management.
• Strong ability to drive verification methodologies is a highly desired for 10+ yrs candidates.
• Exposure to pre silicon validation/emulation is an added advantage.

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