About this role
We are seeking an experienced DFT Engineer (7–12 years) with strong hands-on expertise in Scan Insertion, ATPG, and Gate-Level Simulation (GLS) for complex SoC designs. The candidate will be responsible for implementing and verifying scan architectures, performing scan insertion, generating and analyzing ATPG patterns for stuck-at and transition faults, and executing GLS with and without SDF for DFT validation. The role requires close collaboration with RTL, physical design, and test teams to ensure high fault coverage, clean DFT signoff, and timely tape-out support. Proficiency with industry-standard DFT tools (Mentor/Siemens Tessent, Synopsys, or Cadence), solid Verilog/SystemVerilog skills, and the ability to debug DFT and GLS issues independently are essential. Prior experience supporting pre- and post-silicon activities is a plus.
#LI-9415Jobs Hindustan copied this listing from NXP Semiconductors' official careers site on 30 October 2026 and checked it again 1 November at 5:47 am IST. NXP Semiconductors never asks candidates for money. If anyone does, it is a scam.
Apply on NXP Semiconductors' site
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